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rev. 1.31 8/13 copyright ? 2013 by silicon laboratories SI3402 SI3402 f ully - integrated 802.3- compliant p o e pd i nterface and l ow -emi s witching r egulator features applications description the SI3402 integrates all power management and control functions required in a power-over-ethernet (poe) powered device (pd) application. the SI3402 converts the high voltage supplied over the 10/100/1000base-t ethernet connection into a regulated, low-voltage output supply. the optimized architecture of the SI3402 minimizes the solution footprint, reduces external bom cost, and enables the use of low-cost external components while maintaining high performance. the SI3402 integrates the required diode bridges and transient surge suppressor, thus enabling direct connection of the ic to the ethernet rj-45 connector. the switching power fet and all associated functions are also integrated. the integrated switching regulator supports isolated (flyback) and non-isolated (buck) converter topologies. the SI3402 supports ieee std 802.3? 2008 including the ieee std 802.3at-2009 amendment for the case of single-event classification. standard external resistors connected to the SI3402 provide the proper 802.3 signatures for the detection function and programming of the classification mode. startup circuits ensure well-controlled initial operation of both the hotswap switch and the voltage regulator. the SI3402 is available in a low-profile, 20-pin, 5 x 5 mm qfn package. while the SI3402 is designed for applications up to 10 w, it can be used for higher power applications (up to approximately 15 w). see also ?an313: using the SI3402 in high power applications? for more information. ? ieee 802.3 standard-compliant solution, including pre-standard (legacy) poe support ? highly-integrated ic enables compact solution footprints ?? minimal external components ?? integrated diode bridges and transient surge suppressor ?? integrated switching regulator controller with on-chip power fet ?? integrated dual current-limited hotswap switch ? programmable classification circuit ? incorporates switcher emi- reduction techniques. ? supports non-isolated and isolated switching topologies ? comprehensive protection circuitry ?? transient overvoltage protection ?? undervoltage lockout ?? early power-loss indicator ?? thermal shutdown protection ?? foldback current limiting ? low-profile 5 x 5 mm 20-pin qfn ? rohs-compliant ? voice over ip telephones and adapters ? wireless access points ? security cameras ? point-of-sale terminals ? internet appliances ? network devices ? high power applications ordering information: see page 18. pin assignments 5x5mm qfn (top view) erout ssft rdet hso rcl sp1 sp2 vposf ct1 ploss isossft vdd 5678 9 10 1516 20 19 18 17 1 2 3 4 11 12 13 14 vneg vssa vposs vss1 swo vss2 fb vneg (pad) ct2
SI3402 2 rev. 1.31 functional block diagram detection & classification hotswap switch & current limit hotswap control & common bias pwm control and emi limiting switching fet rectification & protection ct1 ct2 sp1 sp2 vposf vneg rdet rcl hso vdd ploss vss1 swo erout fb ssft isossft vss2 vposs vssa
SI3402 rev. 1.31 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schemati cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.2. pd hotswap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3. switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. recommended land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8. device marking diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
SI3402 4 rev. 1.31 1. electrical specifications table 1. recommended operating conditions description symbol min typ max units |ct1 ? ct2| or |sp1 ? sp2| vport 2.8 ? 57 v ambient operating temperature ta ?40 25 85 c note: unless otherwise noted, all voltages referenced to vneg. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typi cal values apply at nominal supply voltage and ambient temperature unless otherwise noted. table 2. absolute maximum ratings 1 type description rating unit voltage ct1 to ct2 2 ?82 to 82 v sp1 to sp2 2 ?82 to 82 vpos 3 ?0.7 to 80 hso ?0.7 to 80 v ss1 , v ss2 , or v ssa ?0.7 to 80 v ss1 to v ss2 or v ssa ?0.3 to 0.3 swo 4 ?0.7 to 86 ploss to vpos 3 ?80 to 0.7 rdet ?0.7 to 80 vdd to vss1, vss2, or vssa ?0.3 to 5 current ct1, ct2, sp1, sp2 ?5 to 5 a vpos 3 ?5 to 5 ambient temperature storage ?65 to 150 c operating ?40 to 85 notes: 1. unless otherwise noted, all voltages referenced to vneg . permanent device damage may occur if the maximum ratings are exceeded. functional operation should be restricted to those conditions specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may adversely affect device reliability. 2. transient surge is defined in iec60060 as a 1000 v impuls e of either polarity applied across ct1?ct2 or sp1?sp2. the shape of the impulse shall have a 300 ns full rise time and a 50 s half fall time, with 201 ? source impedance. 3. vpos is equal to vposf and vposs tied together for test condition purposes. 4. swo is referenced to v ss1 and v ss2 , which are normally tied together.
SI3402 rev. 1.31 5 table 3. surge immunity ratings 1,2,3 type description rating unit cde 4 cable discharge event tolerance ?3.5 to 3.5 kv esd (system-level) air discharge (iec 61000-4-2) ?16.5 to 16.5 kv contact discharge (iec 61000-4-2) ?8 to 8 kv esd (cdm) jedec (jesd22-c101c) ?750 to 750 v esd (hbm) jedec (jesd22-a114e) ?2000 to 2000 v telephony voltage compatibility ieee 802.3, clause 33.5.6 175 vp notes: 1. permanent device damage may occur if the maximum ratings are exceeded. functional operation should be restricted to those conditions specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may adversely affect device reliability. 2. for more information rega rding system-level surge tolera nce, refer to ?an315: robust electrical surge immunity for poe pds through integrated protection?. 3. designs must be compliant with the pcb layout and exte rnal component recommendations outlined in the SI3402 evb user guide and an296. 4. j. deatherage and d. jones, ?multiple factors trigger ca ble discharge events in ethernet lans,? electronic design dec. 4, 2000.
SI3402 6 rev. 1.31 table 4. electrical characteristics parameter description min typ max unit vport detection 2.7 ? 11 v classification 14 ? 22 uvlo disabled (supply turns on) ??42 uvlo enabled (supply turns off) 30 ? 36 transient surge 1 62 ? 79 input offset current vport < 10 v ? ? 10 a diode bridge leakage vport = 57 v ? ? 25 a iport classification 2 class 0 0 ? 4 ma class 1 9 ? 12 class 2 17 ? 20 class 3 26 ? 30 class 4 36 ? 44 iport operating current 3 36 v < vport < 57 v ? 2 3.1 ma current limit 4 inrush ? 140 ? ma operating 470 ? 680 ma hotswap fet on-resistance + r sense 36 v < vport < 57 v 0.5 ? 1.5 ? power loss vport threshold 27 30 33 v switcher frequency ? 350 ? khz maximum switcher duty cycle 5 isossft connected to vdd ?50? % switcher output transient voltage swo voltage with static load ??80 v swo voltage with switched load ??86 v switching fet on-resistance 0.3 ? 0.86 ? regulated feedback @ pin fb 6 dc avg. ? 1.23 ? v notes: 1. transient surge defined in iec60060 as a 1000 v impulse of either polarity applied to ct1?ct2 or sp1?sp2. the shape of the impulse shall have a 300 ns full rise time and a 50 s half fall time with 201 ? source impedance. 2. the classification currents are g uaranteed only wh en recommended rclass resistors ar e used, as specified in table 10. 3. iport includes full operating current of switching regulator controller. 4. the pd interface includes dual-level input current limit. at turn-on, before the hso load capacitor is charged, the current limit is set at the inrush level. after the capa citor has been charged within ~1.25 v of vneg, the operating current limit is engaged. this higher current limit remains ac tive until the uvlo lower limit has been tripped or until the hotswap switch is sufficiently current-limit ed to cause a foldback of the hso voltage. 5. see ?an296: using the si3400/1/2 poe pd controller in is olated and non-isolated designs? for more information. 6. applies to non-isolated applications only (vout on schematic in figure 1).
SI3402 rev. 1.31 7 regulated output voltage tolerance 6 output voltage tolerance @ vout ?5 ? 5 % vdd accuracy @ 0.8 ma 36 v < vport < 57 v 4.5 ? 5.5 v softstart charging current ssft pin ? 25 ? a isossft pin ? 13 ? a thermal shutdown junction temperature ? 160 ? oc thermal shutdown hysteresis ? ? 25 oc table 5. total power dissipation description test condition min typ max unit power dissipation vport = 50 v, v out =5v, 2a ?1.2? w power dissipation* vport = 50 v, v out = 5 v, 2 a w/ diode bridges bypassed ?0.7? w *note: silicon laboratories recommends the on-chip diode bridges be bypassed when output power requirements are >7 w or in thermally-constrained applications. for more information, see ?an313: using the SI3402 in high power applications?. table 6. package thermal characteristics parameter symbol test condition typ unit thermal resistance (junction to ambient) ? ja still air; assumes a minimum of nine thermal vias are connected to a 2 in 2 heat spreader plane for the package ?pad? node (vneg). 44 c/w table 4. electrical characteristics (continued) parameter description min typ max unit notes: 1. transient surge defined in iec60060 as a 1000 v impulse of either polarity applied to ct1?ct2 or sp1?sp2. the shape of the impulse shall have a 300 ns full rise time and a 50 s half fall time with 201 ? source impedance. 2. the classification currents are g uaranteed only wh en recommended rclass resistors ar e used, as specified in table 10. 3. iport includes full operating current of switching regulator controller. 4. the pd interface includes dual-level input current limit. at turn-on, before the hso load capacitor is charged, the current limit is set at the inrush level. after the capa citor has been charged within ~1.25 v of vneg, the operating current limit is engaged. this higher current limit remains ac tive until the uvlo lower limit has been tripped or until the hotswap switch is sufficiently current-limit ed to cause a foldback of the hso voltage. 5. see ?an296: using the si3400/1/2 poe pd controller in is olated and non-isolated designs? for more information. 6. applies to non-isolated applications only (vout on schematic in figure 1).
SI3402 8 rev. 1.31 2. typical application schematics figure 1. schematic?class 0 with non-isolated 5 v output* *note: this is a simplified schematic. see ?an296: using the si 3400/1/2 poe pd controller in isolated and non-isolated designs? for more details and complete application schematics. table 7. component listing?class 0 with 5 v output item type value toler. rating notes c1 capacitor 15 f 20% 100 v switcher s upply capacitor. several paral- lel capacitors are used for lower esr. c2 capacitor 0.1 f 20% 100 v pd input supply capacitor. c3 capacitor 1000 f 20% 10 v switcher load capacitor - 1000 f in par- allel with and x5r 22 f for lower esr. c4 capacitor 0.1 f 20% 16 v vdd bypass capacitor. c5 capacitor 0.1 f 10% 16 v softstart capacitor. c6 capacitor 3.3 nf 10% 16 v compensation capacitor. c7 capacitor 150 pf 10% 16 v compensation capacitor. r1 resistor 25.5 k ? 1% 1/16 w detection resistor. r2 resistor 8.66 k ? 1% 1/16 w feedback resistor divider. r3 resistor 2.87 k ? 1% 1/16 w feedback resistor divider. r4 resistor 30.1 k ? 1% 1/16 w feedback compensation resistor. d1 diode 100 v schottky diode; part no. pds5100. l1 inductor 33 h 20% 3.5 a coilcraft part no. do5010333. c1 SI3402 rj-45 to ethernet phy r1 vneg rcl rdet ct1 ct2 sp1 sp2 vposf hso vss1 l1 swo d1 r2 r3 fb ploss ssft erout vout vdd c2 c3 c5 isossft vss2 vposs c6 r4 c4 vssa c7
SI3402 rev. 1.31 9 figure 2. schematic?class 1 with isolated 5.0 v output* *note: this is a simplified schematic. see ?an296: using the si 3400/1/2 poe pd controller in isolated and non-isolated designs? for more details and complete application schematics. table 8. components?class 1 with isolated 5.0 v output item type value toler. rating notes c1 capacitor 15 f 20% 100 v switcher supply capacitor. several paral- lel capacitors are used for lower esr. c2 capacitor 0.1 f 20% 100 v pd input supply capacitor. c3 capacitor 1100 f 20% 10 v switcher load capacitor. 100 f in paral- lel 1000 f and optional 1 h inductor for additional filtering. c4 capacitor 15 nf 10% 16 v feedback compensation. c5 capacitor 220 nf 10% 16 v feedback compensation. c7 capacitor 0.1 f 20% 16 v vdd bypass capacitor. c8 capacitor 1 f 20% 16 v isolated mode soft start (tie isossft to vdd if this feature is not used). r1 resistor 25.5 k ? 1% 1/16 w detection resistor. r2 resistor 4.99 k ? 1% 1/16 w pull-up resistor. r3 resistor 100 ? 1% 1/16 w feedback compensation resistor. r4 resistor 10 k ? 1% 1/16 w feedback compensation resistor. r5 resistor 2.05 k ? 1% 1/16 w pull-up resistor. r6 resistor 36.5 k ? 1% 1/16 w feedback resistor divider. r7 resistor 12.1 k ? 1% 1/16 w feedback resistor divider. r8 resistor 127 ? 1% 1/16 w classification resistor. d1 diode 10 a 40 v schottky diode; part no. pn pds1040. d2 diode 1 a 100 v snubber diode (1n4148) d3 diode 15 v 9 a snubber diode (dflt15a) t1 transformer 40 h coilcraft part number fa2672 (5 v). ps2911 optocoupler tlv431 voltage reference c1 SI3402 rj-45 to ethernet phy vneg rcl rdet ct1 ct2 sp1 sp2 c2 hso vss1 swo c3 ssft ploss d1 r5 r7 r6 tlv431 ps2911 t1 r2 fb vdd erout vout r1 isossft vss2 r3 c5 c4 r4 c7 vposf vposs r8 vssa d2 d3 c8
SI3402 10 rev. 1.31 3. functional description the SI3402 consists of two major functions: a hotswap controller/interface and a complete pulse-width- modulated switching regulator (controller and power fet). 3.1. overview the hotswap interface of the SI3402 provides the complete front end of an 802.3-compliant pd. the SI3402 also includes two full diode bridges, a transient voltage surge suppressor, detection circuit, classification current source, and dual-level hotswap current limiting switch. this high level of integration enables direct connection to the rj-45 connector, simplifies system design, and provides significant advantages for reliability and protection . the SI3402 requires only four standard external components (detection resistor, optional classification resistor, load capacitor, and input capacitor) to create a fully 802.3- compliant interface. for more information about supporting higher-power applications, see ?an313: using the SI3402 in high power applications? and ?an314: power combining circuit for poe for up to 18.5 w output?. the SI3402 integrates a complete pulse-width modulated switching regulator that includes the controller and power fet. the switching regulator utilizes a constant freque ncy pulse-width modulated controller optimized for all possible load conditions in poe applications. the regulator integrates a low on- resistance (ron) switching power mosfet that minimizes power dissipation, increases over all regulator efficiency, and simplifies system design. an integrated error amplifier, precision reference, and programmable soft-start current source prov ide the flexibility of using a non-isolated buck regulator topology or an isolated flyback regulator topology. the SI3402 is designed to operate with both 802.3- compliant power sourcing equipment (pse) and pre- standard (legacy) pses that do not adhere to the 802.3 specified inrush cu rrent limits. the SI3402 is compatible with compliant and legacy pses because it uses two levels for the hotswap current limits. by setting the initial inrush current limit to a lo w level, a pd based on the SI3402 minimizes the current drawn from either a compliant or legacy pse during startup. after powering up, the SI3402 automatically switches to a higher-level current limit, thereby allowing the pd to consume up to 12.95 w (the max power allowed by the 802.3 specification). the inrush current limit specified by the 802.3 standard can generate high transient power dissipation in the pd. by properly sizing the devices and implementing on- chip thermal protection, the SI3402 can go through multiple turn-on sequence s without overheating the package or damaging the device. the switching regulator power mosfet has been conservatively designed and sized to withstand the high peak currents created when converting a high-voltage, low-current supply into a low-voltage, high-current supply. excessive power cycling or short circuit faults will engage the thermal overload protection to prevent the onboard power mosfets from exceeding their safe and reliable operating ranges. 3.2. pd hotswap controller the SI3402 hotswap controller changes its mode of operation based on the input voltage applied to the ct1 and ct2 pins or the sp1 and sp2 pins, the 802.3- defined modes of operation, and internal controller requirements. table 9 defines the modes of operation for the hotswap interface. figure 3. hotswap block diagram diode bridges and protection detection control on off vposf vneg ct1/sp1 ct2/sp2 0 v 12 v rdet classification control on off 12 v 22 v rcl central bias bandgap ref 10 v 5 v 1.23 v current limit hi/lo hotswap control on off 39 v 32 v switcher startup & bias iabs itc vref hso power loss detector ploss ssft vposs isossft
SI3402 rev. 1.31 11 3.2.1. rectification diode bridges and surge suppressor the 802.3 specification defines the input voltage at the rj-45 connector of the pd with no reference to polarity. in other words, the pd must be able to accept power of either polarity at each of its inputs. this requirement necessitates the use of two sets of diode bridges, one for the ct1 and ct2 pins and one for the sp1 and sp2 pins to rectify the voltage. furthermore, the standard requires that a pd withstand a high-voltage transient surge consisting of a 1000 v common-mode impulse with 300 ns rise time and 50 s half fall time. typically, the diode bridge and the surge suppressor have been implemented externally, adding cost and complexity to the pd system design. the diode bridge* and the surge suppressor have been integrated into the SI3402, thus reducing system cost and design complexity. *note: silicon laboratories recommends that on-chip diode bridges be bypassed when >7 w of output power is required. by integrating the diode bridges, the SI3402 gains access to the input side of the diode bridge. monitoring the voltage at the input of the diode bridges instead of the voltage across the load capacitor provides the earliest indication of a power loss. this true early power loss indicator, ploss , provides a local microcontroller time to save states and shut down gracefully before the load capacitor discharges below the minimum 802.3- specified operating voltage of 36 v. integration of the surge suppressor enables optimization of the clamping voltage and guarantees protection of all connected circuitry. as an added benefit, the transient surge suppressor, when tripped, actively disables the hotswap interface and switching regulator, preventing downstream circuits from encountering the high-energy transients. 3.2.2. detection in order to identify a device as a valid pd, a pse will apply a voltage in the range of 2.8 to 10 v on the cable and look for the 25.5 k ? signature resistor. the SI3402 will react to voltages in th is range by connecting an external 25.5 k ? resistor between vpos and vneg. this external resistor and internal low-leakage control circuitry create the proper signature to alert the pse that a valid pd has been detected and is ready to have power applied. the internal hotswap switch is disabled during this time to prevent the switching regulator and attached load circuitry from generating errors in the detection signature. since the SI3402 integrates the diode bridges, the ic can compensate for the voltage and resistance effects of the diode bridges. the 802.3 specification requires that the pse use a multi-point, ? v/ ? i measurement technique to remove the diode-induced dc offset from the signature resistance measurement. however, the specification does not address the diode's nonlinear resistance and the error induced in the signature resistor measurement. since the diode's resistance appears in series with the signature resistor, the pd system must find some wa y of compensating for this error. in systems where the diode bridges are external, compensation is difficult and suffers from errors. since the diode bridges are integrated in the SI3402, the ic can compensate for this er ror by offsetting resistance across all operating conditions and thus meeting the 802.3 requirements. an ad ded benefit is that this function can be tested during the ic?s automated testing step, guaranteeing system compliance when used in the final pd application. for more information about supporting higher-power applications (above 12.95 w), see ?an313: using the SI3402 in high power applications? and ?an314: power combining circuit for poe for up to 18.5 w output?. 3.2.3. classification once the pse has detected a valid pd, the pse may classify the pd for one of five power levels or classes. a class is based on the expected power consumption of the powered device. an external resistor sets the nominal class current that can then be read by the pse to determine the proper power requirements of the pd. when the pse presents a fixed voltage between 15.5 v and 20.5 v to the pd, the SI3402 asserts the class current from vpos throug h the rcl resistor. the resistor values associated with each class are shown in table 10. table 9. hotswap interface modes input voltage (|ct1-ct2| or |sp1-sp2|) SI3402 mode 0 to 2.7 v inactive 2.7 to 11 v detection signature 11 to 14 v detection turns off and internal bias starts 14 to 22 v classification signature 22 to 42 v transition region 42 up to 57 v switcher operating mode (hysteresis limit based on rising input voltage) 57 down to 36 v switcher operating mode (hysteresis limit based on falling input voltage)
SI3402 12 rev. 1.31 the 802.3 specification limits the classification time to 75 ms to limit the power diss ipated in the pd. if the pse classification period e xceeds 75 ms and the die temperature rises above the thermal shutdown limits, the thermal protection ci rcuit will engage and disable the classification current source in order to protect the SI3402. the SI3402 stays in classification mode until the input voltage exceeds 22 v (the upper end of its classification operation region). 3.2.4. under voltage lockout the 802.3 standard specifies the pd to turn on when the line voltage rises to 42 v and for the pd to turn off when the line voltage falls to 30 v. the pd must also maintain a large on-off hysteresis region to prevent wiring losses between the pse and the pd from causing startup oscillation. the SI3402 incorporates an undervoltage lockout (uvlo) circuit to monitor the line voltage and determine when to apply power to the integrated switching regulator. before the power is applied to the switching regulator, the hotswap switch output (hso) pin is high- impedance and typically fo llows vpos as the input is ramped (due to the discharged switcher supply capacitor). when the input voltage rises above the uvlo turn-on threshold, the SI3402 begins to turn on the internal hotswap power mosfet. the switcher supply capacitor begins to charge up under the current limit control of the SI3402, and the hso pin transitions from vpos to vneg. the si 3402 includes hysteretic uvlo circuits to maintain power to the load until the input voltage falls below the uvlo turn-off threshold. once the input voltage falls below 30 v, the internal hotswap mosfet is turned off. 3.2.5. dual current limit and switcher turn-on the SI3402 implements dual current limits. while the hotswap mosfet is charging the switcher supply capacitor, the SI3402 mainta ins a low current limit. the switching regulator is disabled until the voltage across the hotswap mosfet becomes sufficiently low, indicating the switcher supply capacitor is almost completely charged. when this threshold is reached, the switcher is activated, and the hotswap current limit is increased. this threshold also has hysteresis to prevent systemic oscillation as the switcher begins to draw current and the current limit is increased, which allows resistive losses in the cable to effectively decrease the input supply. the SI3402 stays in a high-level current limit mode until the input voltage drops below the uvlo turn-off threshold or excessive power is dissipated in the hotswap switch. this dual le vel current limit allows the system designer to design powered devices for use with both legacy and compliant poe systems. an additional feature of the dual current limit circuitry is foldback current limiting in the event of a fault condition. when the current limit is sw itched to the higher level, 400 ma of current can be drawn by the pd. should a fault cause more than this current to be consumed, the voltage across the hotswap mosfet will increase to clamp the maximum amount of power consumed. the power dissipated by the mosfet can be very high under this condition. if the fault is very low impedance, the voltage across the ho tswap mosfet will continue to rise until the lower cu rrent limit level is engaged, further reducing the dissipated power. if the fault condition remains, the thermal overload protection circuitry will eventually engage and sh ut down the hotswap interface and switching regulator. the foldback current limiting occurs much faster than the thermal overload protection and is, therefore, necessary for comprehensive protection of the hotswap mosfet. table 10. class resistor values class usage peak power levels nominal class current rcl resistor (1%, 1/16 w) 0 default 0.44 to 12.95 w < 4 ma > 1.33 k ? (or open circuit) 1 optional 0.44 to 3.84 w 10.5 ma 127 ? 2 optional 3.84 to 6.49 w 18.5 ma 69.8 ? 3 optional 6.49 to 12.95 w 28 ma 45.3 ? 4 poe+ 12.95 to 17 w 40 ma 30.9 ?
SI3402 rev. 1.31 13 3.2.6. power loss indicator a situation can occur in which power is lost at the input of the diode bridge and the hotswap controller does not detect the fault due to the vpos to vneg capacitor maintaining the voltage. in such a situation, the pd can remain operational for hundreds of microseconds despite the pse having removed the line voltage. if it is recognized early enough, the time from power loss to power failure can provide valuable time to gracefully shut down an application. due to integration of the diode bridges, the SI3402 is able to instantaneously detect the removal of the line voltage and provide that early warning signal to the pd application. the ploss pin is an open drain output that pulls up to vpos when a line voltage greater than 27 v is applied. when the line vo ltage falls below 27 v, the output becomes high-impedance, allowing an external pull-down resistor to change the logic state of ploss. the benefit of this indicato r is that the powered device may include a microcontroller that can quickly save its memory or operational state before draining the supply capacitors and powering itself down. this feature can help improve overall manage ability in applications, such as wireless access points. 3.3. switching regulator power over ethernet (poe) applications fall into two broad categories, isolated and non-isolated. non- isolated systems can be used when the powered device is self-contained and does not provide external conductors to the user or another application. non- isolated applications includ e wireless access points and security cameras. in these applications, there is no explicit need for dc isolation between the switching regulator output and the hotswap interface. an isolated system must be used when the powered device interfaces with other self-powered equipment or has external conductors accessible to the user or other applications. for proper operation, the regulated output supply of the switching regulator must not have a dc electrical path to the hotswap interface or switching regulator primary side. isolated applications include point-of-sale terminals where the user can touch the grounded metal chassis. the application determines the converter topology. an isolated application will requ ire a flyback transformer- based switching topology while a non-isolated application can use an inductor-based buck converter topology. in the isolated ca se, dc isolation is achieved through a transformer in the forward path and a voltage reference plus opto-isolator in the feedback path. the application circuit shown in figure 2 is an example of such a topology. the non-isolated application in figure 1 makes use of a single inductor as the energy conversion element, and the feedback signal is directly supplied into the internal error amplifier. as can be seen from the application circuits, the isolated topology has an increased number of components, thus increasing the bill of materials (b om) and syste m footprint. to optimize cost and ease implementation, each application should be evaluated for its isolated or non- isolated requirements. figure 4. switcher block diagram vss1 switch drive switcher startup & bias iabs itc vref pulse- width modulator oscillator error amplifier erout fb ssft vdd swo vposs hso vss2 vposf vssa isossft
SI3402 14 rev. 1.31 3.3.1. switcher startup the switching regulator is disabled until the hotswap interface has both identifi ed itself to the pse and charged the supply capacitor needed to filter the switching regulator's high-current transients. once the supply capacitor is charged, the hotswap controller engages the internal bias currents and supplies used by the switcher. additionally, the soft-start current begins to charge the external soft-start capacitor. the voltage developed across the soft-start capacitor serves as the error amplifier's reference in the non- isolated application. rampi ng this voltage slowly allows the switching regulator to bring up the regulated output voltage in a controlled man ner. controlling the initial startup of the regulated voltage restrains power dissipation in the switching fet and prevents overshoot and ringing in the output supply voltage. in the isolated mode, a capacitor connected between pins isossft and vssa slo wly ramps the duty cycle clamp in the pwm circuit. tie th is pin to vdd if it is not used. 3.3.2. switching regulator operation the switching regulator of the SI3402 is constant- frequency, pulse-width-modulated (pwm), and controller integrated wit h switching power fets optimized for the output power range defined by the 802.3 specification. once the hotswap interface has ensured proper turn-on of the switching regulator cont roller, the switcher is fully operational. an in ternal free-runni ng oscillator and internal precision voltage reference are fed into the pulse-width modulator. the output of the error amplifier (either internal for non-isolated applications or external for isolated applications) is also routed into the pwm and determines the slicing of the oscillator. the pwm controls the switching fet drive circuitry. a significant advantage of integrating the switching power fet onto the same monolithic ic as the switching regulator controller is the ab ility to precisely adjust the drive strength and timing to the fet's sizable gate, resulting in high regulator efficiency. furthermore, current-limiting circuitry prevents the switching fet from sinking too much curr ent, dissipating too much power, and becoming damaged. thermal overload protection provides a seco ndary level of protection. the flexibility of the SI3402's switching regulator allows the system designer to realize either the isolated or non- isolated application circuitry using a single device. in operation, the integration of the switching fet allows tighter control and more ef ficient operation than a general-purpose switching regulator coupled with a general-purpose external fet. 3.3.3. flyback snubber extremely high voltages can be generated by the inductive kick associated with the leakage inductance of the primary side of the flyback transformer used in isolated applications. refer to ?an296: using the si3400/1/2 poe pd controller in isolated and non-isolated designs? for more information on the snubber.
SI3402 rev. 1.31 15 4. pin descriptions table 11. SI3402 pin descriptions (top view) pin# name description 1 erout error-amplifier output and pwm input; directly connected to opto-couple r in isolated application. 2ssft soft-start output pin ramps voltage across external soft-start capacitor to allow switcher to ramp output slowly. 3 vdd 5 v supply rail for switcher ; provides drive for opto-coupler. 4 isossft isolated mode soft start enable input. 5ploss early power loss indicator; open drain output is pulled to vpos when vport is applied. 6 rdet input pin for external precision detection resist or; also used for establishing absolute current reference. 7 hso hotswap switch output; connects to vneg through hotswap switch. 8 rcl input pin for external prec ision classification resistor; fl oat if optional rclass is unused. 9, pad vneg rectified high-voltage supply, negative rail. must be connected to thermal pad node (vneg) on package bottom. this thermal pad must be connected to vneg (pin #9) as well as a 2 in 2 heat spreader plane using a minimum of nine thermal vias. 10 sp2 high-voltage supply input from spare pair; polar ity-insensitive. 11 sp1 high-voltage supply input from spare pair; polar ity-insensitive. 12 vposf rectified high-voltage suppl y, positive rail (force node) 13 ct2 high-voltage supply input from center tap of ethernet transformer ; polarity-insensitive. 14 ct1 high-voltage supply input from center tap of ethernet transformer ; polarity-insensitive. 15 vssa analog ground. 16 vposs rectified high-voltage s upply, positive rail sense node. 17 vss1 negative supply rail for sw itcher; externally tied to hso. 18 swo switching transistor output; drain of switching n-fet. 19 vss2 negative supply rail for sw itcher; externally tied to hso. 20 fb regulated feedback input in non-isolated application. erout ssft rdet hso rcl sp1 sp2 vposf ct1 ploss isossft vdd 5678 9 10 1516 20 19 18 17 1 2 3 4 11 12 13 14 vneg vssa vposs vss1 swo vss2 fb vneg (pad) ct2
SI3402 16 rev. 1.31 5. package outline figure 5 illustrates the package details for the SI3402. table 12 lists the values for the dimensions shown in the illustration. figure 5. 20-lead quad flat no-lead package (qfn) table 12. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.25 0.30 0.35 d 5.00 bsc. d2 2.60 2.70 2.80 e 0.80 bsc. e 5.00 bsc. e2 2.60 2.70 2.80 l 0.50 0.55 0.60 l1 0.00 ? 0.10 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.10 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vhhb-1.
SI3402 rev. 1.31 17 6. recommended land pattern figure 6. SI3402 recommended land pattern table 13. pcb land pattern dimensions symbol min nom max p1 2.70 2.75 2.80 p2 2.70 2.75 2.80 x1 0.25 0.30 0.35 y1 0.90 0.95 1.00 c1 4.70 c2 4.70 e0 . 8 0 notes: general 1. all dimensions shown are in m illimeters (mm) unle ss otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. solder mask design 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and electro-polished sten cil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 8. a 2x2 array of 1.2 mm square openings on 1.4 mm pitch should be used for the center ground pad. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ?
SI3402 18 rev. 1.31 7. ordering guide part number 1,2 package temp range recommended maximum output power 3 SI3402-a-gm 20-pin qfn, pb-free; rohs compliant ?40 to 85 c < 10 w (ieee 802.3 systems) 17 w (proprietary high power) notes: 1. ?x? denotes product revision. 2. add an ?r? at the end of the part number to denote tape and reel option. 3. refer to ?an313: using the SI3402 in high power applicatio ns? and ?an314: power combining circuit for poe for up to 18.5 w output? for more information about using the SI3402 in higher power applications.
SI3402 rev. 1.31 19 8. device marking diagram figure 7. device marking diagram table 14. device marking table line # text value description 1 SI3402 base part number. this is not the ?o rdering part number? since it does not contain a specific revision. refer to "7. ordering guide" on page 18 for complete ordering information. 2g m g = industrial temperature range. m = qfn package. 3 tttttt trace code (assigned by the assembly subcontractor). 4 circle = 20 mils diameter (bottom-left justified) pin 1 identifier. yy assembly year. ww assembly week. ?
SI3402 20 rev. 1.31 d ocument c hange l ist revision 1.0 to revision 1.1 ? added "6. recommended land pattern" on page 17. revision 1.1 to revision 1.2 ? added "8. device marking diagram" on page 19. revision 1.2 to revision 1.3 ? deleted old table 2 on page 4. ? updated table 2, ?absolute maximum ratings 1 ,? on page 4. ? updated table 3, ?surge immunity ratings 1 , 2 , 3 ,? on page 5. ? updated table 4, ?electri cal characteristics,? on page 6. revision 1.3 to revision 1.31 ? updated table 11, ?SI3402 pin descriptions (top view),? on page 15.
SI3402 rev. 1.31 21 n otes :
SI3402 22 rev. 1.31 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive patent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibili ty for errors and omissions, and disclaim s responsibility for any consequences resu lting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warran- ty, representation or guarantee regarding t he suitability of its products for any par ticular purpose, nor does silicon laborato ries assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, in cluding without limitation consequential or incidental damages . silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmle ss against all claims and damages.

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